Video signal transmitter

ABSTRACT

To provide a video signal transmission apparatus capable of correctly transmitting a digital video signal. A PLL circuit  5  has a first cutoff frequency lower than the frequency of a horizontal synchronization signal contained in a digital video signal S 9.  has the characteristics of causing attenuation of a signal of the frequency higher than the first cutoff frequency, performs PLL processing for a dot clock signal S 14  for identifying one pixel&#39;s worth of data of the digital video signal S 9,  and generates a transmission clock signal  55  of the frequency N (integer of 2 or more) times the first dot clock signal S 14.  The PLLL circuit  6  has a second cutoff frequency higher than the frequency of the horizontal synchronization signal, tracks a signal of a frequency lower than the related second cutoff frequency, performs the PLL processing on the serial signal S 2  input via the transmission cable  4,  and generates a transmission clock signal S 6.

TECHNICAL FIELD

The present invention relates to a video signal transmission apparatusfor transmitting a multi-bit, digital, video signal converted to aserial signal.

BACKGROUND ART

For example, the technique of converting a multi-bit, digital, videosignal into a serial signal and transmitting the same has been used inthe trunk communications, LAN (Local Area Network), etc.

When transmitting a digital signal in this way, the transmittermultiplies the synchronization signal contained in a multi-bit digitalsignal, that is, the clock signal, to generate a clock signal fortransmission of serial signal and multiplexes the multi-bit digitalsignal to generate a serial signal.

Further, the receiver uses a clock signal extracted from a frequencycomponent contained in the received serial signals using a PLL (PhaseLocked Loop) circuit so as to demultiplex the serial signal.

Here, the clock signal for transmission of the serial signal has aconsiderably high frequency compared with the clock signal of themulti-bit digital signal. For this reason, in order to reduce thetransmission error, it is necessary to use a transmission clock signalof a low jitter having a high tire precision.

Accordingly for the transmitter, for example, a low jitter highprecision clock signal output from a crystal oscillator is used as theclock signal of the multi-bit digital signal serving as the base forgenerating the transmission clock.

A liquid crystal display or other display receiving as its input adigital signal, however, sometimes is serially sent an R, G, and Bmulti-bit digital video signal.

Such a digital video signal is comprised by a 12- to 24-bit digitalsignal indicating a color gradation and SYNC (synchronization) signalindicating a synchronization position of an image. These digital signaland SYNC signal are synchronous with a dot clock signal. The colorgradation of one pixel, an element comprising the image, is indicted forevery dot clock signal.

Here, the frequency of the dot clock signal is set to about 25 to 70 MHzin accordance with the total number of pixels of the image.

The above-mentioned digital video signal is generally generated by alarge-sized LSI (large scale integrated circuit) referred to as agraphic accelerator. The dot clock signal generated by the graphicaccelerator contains a phase modulation component in addition to a puresynchronization clock component for the following reasons (1) and (2).

(1) In the graphic accelerator, the clock signal from the crystaloscillator is transformed in frequency by the PLL circuit, but anunnecessary and harmful signal component, that is, spurious noise, leaksout of this PLL circuit. This spurious noise appears as the phasemodulation component of the dot clock signal.

(2) The noise accompanying a large volume of digital signal processinghandled by the graphic accelerator leaks to the dot clock. For example,in the transmission of a R, G, and B digital video signal, the periodfor transmitting the data to be actually displayed as the image and ablanking period for not performing the image display are repeated with acycle of the horizontal synchronization signal. For this reason, astrong phase modulation comprised of the frequency of the horizontalsynchronization signal as a component is contained in the dot clocksignal.

For this reason, the dot clock signal, the phase modulation component ismainly distributed at positions of a fraction to a multiple of thefrequency of the horizontal synchronization signal.

However, there is a problem that if such a phase modulation component iscontained in the dot clock signal, an obstacle occurs in the serialtransmission of the digital video signal and the digital video signalscannot be correctly transmitted.

DISCLOSURE OF THE INVENTION

An object of the present invention is to provide a video signaltransmission apparatus capable of suppressing the influence exerted uponthe transmission clock signal by strong phase modulation having mainlythe frequency of the horizontal synchronization signal as its componentand, thereby, correctly transmitting the digital video signal.

The video signal transmission apparatus according to a first aspect ofthe present invention comprises a first PLL circuit having a firstcutoff frequency lower than a frequency of a horizontal synchronizationsignal contained in a digital video signal, having the characteristicsof causing attenuation of a phase modulation component of a frequencyhigher than the first cutoff frequency, and generating a firsttransmission clock signal of a frequency of N (integer of 2 or more)times a first dot clock signal for identifying one pixel's worth of dataof the digital video signal and phase locked looped to the first dotclock signal; a first conversion means for generating a serial signalfrom a plurality of a parallel input element signals comprising thedigital video signal based on the first dot clock signal and the firsttransmission clock signal; a transmission channel for transmitting theserial signal; a second PLL circuit having a second cutoff frequencyhigher than the frequency of the horizontal synchronization signal,tracking the phase modulation of a frequency lower than the secondcutoff frequency, and generating a second transmission clock signal fromthe serial signal input via the transmission channel; a frequencydivision circuit for dividing the second transmission clock signal 1/Nto generate a second dot clock signal; and, a second conversion meansfor generating a plurality of element signals to be output in parallelform a serial signal input though the transmission channel based on thesecond dot clock signal and the second transmission clock signal.

Preferably, the fist PLL circuit attenuates a phase modulation componentcontained in the first dot clock signal more than higher the frequencyin a frequency region higher than the first cutoff frequency.

More preferably, the second PLL circuit has less of a tracking error thelower the frequency in a frequency region lower than the second cutofffrequency.

Further, the plurality of element signals are digital color signals anda synchronization signal

Further, preferably, N is 4, 18, 24, 28, 30, or 32.

Further, according to a second aspect of the present invention, there isprovided a video signal transmission apparatus for generating andtransmitting a serial signal from a plurality of parallel input elementsignals comprising a digital video signal, comprising a PLL circuithaving a cutoff frequency lower than a frequency of a horizontalsynchronization signal contained in the digital video signal, having thecharacteristic of causing attenuation of a phase modulation component ofa frequency higher than the cutoff frequency, and generating atransmission clock signal of a frequency of N (integer of 2 or more)times a dot clock signal for identifying one pixel's worth of data ofthe digital video signal and phase locked looped to the dot clock signaland a conversion means for generating a serial signal from a pluralityof parallel input elements signals comprising the digital video signalbased on the dot clock signal and the transmission clock signal.

Preferably, the PLLC circuit attenuates a phase modulation componentcontained in the dot clock signal more than the higher the frequency ina frequency region higher then the cutoff frequency.

BRIEF DESCRIPTION OF THE DRAWINGS

The above object and features of the present invention will becomeclearer form the following description given with reference to theappended drawings.

FIG. 1 is a view of the system configuration of an embodiment of adigital, video signal transmission apparatus according to the presentinvention.

FIG. 2 is a view for explaining the relationships among a phasemodulation of an input signal, a modulation component g appearing in anoutput signal, and a relative ratio ε of the tracking error with respectto the phase modulation of the input signal.

FIG. 3A is a view showing the relationships between the frequency andthe intensity of the phase modulation of a litter of a dot clock.

FIG. 3B is a view showing the relationships between the jitter transferand the frequency of a PLL circuit of a transmitter.

FIG. 3C is a view showing the relationship between the phase modulationintensity and the frequency of the jitter contained in a serial signal.

FIG. 3D is a view showing the relationship between a relative trackingerror and the frequency of a PLL circuit of a receiver.

FIG. 3E is a view showing the relationship between the tracking errorand the frequency of the PLL circuit of the receiver.

BEST MODE FOR WORKING THE INVENTION

Below, an embodiment of a digital video signal transmission apparatusaccording to the present invention will be explained.

FIG. 1 is a view of the system configuration of an embodiment of adigital video signal transmission apparatus 1 according to the presentinvention.

As shown in FIG. 1, the digital video signal transmission apparatus 1has, for example, a parallel/serial (P/S/) converter 2, aserial/parallel (S/P) converter 3, and transmission cable 4, a PLLCircuit 5, a PLL circuit 6, and a frequency divider 7.

Here, the parallel!serial converter 2 and the PLL circuit 5 are built ina transmitter arranged at one end of the transmission cable 4. Also, theserial/parallel converter 3. PLL circuit 6, and frequency divider 7 arebuilt in a receiver arranged at the other end of the transmission cable4.

The PLL circuit 5 generates a transmission clock signal S5 having afrequency of a dot clock (DOTCLK) signal S14 by N in synchronizationwith that frequency. In the present embodiment, N is 4.

Note that, as N, other than 4 18, 24, 28, 30, or 32 can be used too.

Also, the PLL circuit 5 has, for example, a cutoff frequency BWP₁, whichis {fraction (1/10)}^(th) or less of the frequency f_(HSYNC) of thehorizontal synchronization signal of a digital video signal S9 andattenuates the phase modulation component of the frequency exceeding thecutoff frequency BWP₁ contained in a dot clock signal S14. Here, in thePLL circuit 5, at a frequency exceeding the cutoff frequency BWP1, thehigher the frequency, the larger the attenuation of the transmissionclock signal 55 with respect to the dot clock signal S14.

When the PLL circuit 5 has a secondary transmission functioncharacteristic, the ratio of the phase of the output signal with respectto the phase of the input signal, that is, the jitter H_(T)(s), isindicated by the following equation (1) $\begin{matrix}\begin{matrix}{{H_{T}(s)} = {{(s)/{\Theta_{o}(s)}}/{\Theta_{i}(s)}}} \\{= {\left( {{2{\zeta \cdot \omega_{n} \cdot s}} + \omega_{n}^{2}} \right)/{\left( {s^{2} + {2{\zeta \cdot \omega_{n} \cdot s}} + \omega_{n}^{2}} \right)\quad.\quad.\quad.}}}\end{matrix} & {\quad (1)\quad}\end{matrix}$

In equation (1), Θ_(o) (s) indicates a Laplace transform of the phase ofthe output signal, and Θ_(o) (S) indicated the Laplace transforms of thephase of the input signal. Also, ζ indicates a damping coefficient, andω_(n) indicates a natural angular frequency.

Here, in the PLL circuit 5, a cutoff frequency BWP₁ (Band Width Point)at which the jitter transfer H_(T) (s) becomes −3 dB is indicated by thefollowing equation (2).

BWP ₁=ω_(n) ^(·)[1+2ζ²+{1+(1+2ζ²)²}^(½)]^(½)

In the PLL circuit 5, the cutoff frequency BWP₁ is set to {fraction(1/10)} times or less of the frequency f_(HSYNC) of the horizontalsynchronization signal, as mention above.

By setting the cutoff frequency BWP₁ to {fraction (1/10)} times or lessthe frequency f_(HSYNC) of the horizontal synchronization signal in thisway, the phase modulation component of the jitter having the frequencyin the vicinity of the frequency f_(HSYNC) of the horizontalsynchronization signal contained in the dot clock signal S14 can notpass much at all through the PLL circuit 5. Namely, the jitter occurringin the serial signal S4 generated based on the dot clock signal S14 canbe suppressed.

Note that the dot clock signal S14 is used when indicating thepunctuation of the data of the color gradation of a pixel of the imageindicated by the digital video signal and is set so as to have afrequency of about 25 to 70 MHz in accordance with the total number ofpixels of the image.

The parallel/serial converter 2 receives as its input a digital P signalS10, a digital G signal S11, a digital B signal S 12, and a SYNC(synchronization) signal S13 compromising the digital video signal S9,performs parallel/serial conversion on these signals based on thetransmission clock signal S5 input from the PLL circuit 5 and the dotclock signal S14, and generates the serial signal S2. Theparallel/serial converter 2 outputs the generated serial signal S2 tothe serial/parallel converter 3 via the transmission cable 4.

The transmission cable 4 is a monitor cable using, for example, copperwire and has a length of, for example, about 0.1 to 20 m.

The PLL circuit 6 tracks the frequency of the serial signal S2 receivedby the receiver via the transmission cable 4 and extracts a transmissionclock signal S6. The PBS circuit 6 outputs the extracted transmissionclock signal S6 to the serial/parallel converter 3 and the frequencydivider 7.

Also, the PLL circuit 6 has, for example, a cutoff frequency BWP₂ of 10times or more of the frequency f_(HSYNC) Of the horizontalsynchronization signal of the digital video signal S9 and tracks thephase modulation component of a frequency of less than the cutofffrequency BWP₂ contained in the serial signal S2.

Here, at below the frequency of the cutoff frequency BWP₂ the lower thefrequency, the smaller the tracking error (the better the tracking).

Namely, the PLL. circuit 6 correctly tracks the serial signal S2 havingthe phase modulation and prevents error from occurring.

FIG. 2 is a view for explaining the relationship among a phasemodulation of the input signal, a modulation component g appearing inthe output signal, and a relative ratio ω of the tracking error withrespect to the phase modulation of the input signal.

As shown in FIG. 2, the relative error ε of the tracking error withrespect to the phase modulation of the input signal is indicated by thefollowing equation (3) when considering the phase modulation as a phaserof a magnitude 1.

Here, a “phaser” is an indicator representing the amplitude and phase ofa sine-wave signal.

ε(ω)={(1-g ^(·)cosΘ)²+(g ^(·)sinΘ)²}^(½)

Note that, g and, in Equation (3) are indicated by following equations(4) and (5).

g=|H_(t)(ω)|  (4)

θ=<|H_(t)(ω)|  (5)

In the PLL circuit 6, the lower the frequency of the serial signal S2,the more the angle Θ approaches 0, the more the length of the modulationcomponent g appearing in the output signal approaches 1, and the more εapproaches 0. Namely, the output signal tracks the input signal well. Onthe other hand, the higher the frequency of the serial signal S2, thelarger the angle Θ, the more the modulation component g appearing in theoutput signal approaches 0, and the more ε approaches 1. Namely, thetracking error is large, and the output signal substantially does nottrack the input signal.

The PLL circuit 6 sets the cutoff frequency BWP, found from Equation (2)in the same way as the cutoff frequency BWP₁ to 10 times or more thefrequency f_(HSYNC) of the horizontal synchronization signal, unlike thePLL, circuit 5.

By setting the cutoff frequency BWP₂ to 10 times or more the frequencyf_(HSYNC) of the horizontal synchronization signal in this way, it ispossible to get the large-phase modulation component contained in theserial signal S2 to remain at the transmission clock signal S6 and tosuppress the tracking error of the transmission clock signal S6 withrespect to the serial signal S2. Namely, occurrence of error at the timeof transmission can be suppressed.

The frequency divider 7 generates a dot clock (DOTCLK) signal S7obtained by dividing the frequency of the transmission clock signal S6by N times and outputs this to the serial/parallel converter 3.

The serial/parallel converter 3 performs serial/parallel conversion onthe serial signal S4 received via the transmission cable 4 based on thetransmission clock signal S6 and the dot clock signal S7 and outputs adigital R signal S20, a digital G signal S21, a digital B signal S22,and a SYNC (synchronization) signal S23 comprising a digital videosignal S19; in parallel.

Below, an explanation will be made of the operation of the digital,video signal, transmission apparatus 1 by giving a concrete example.

FIG. 3A is a view showing the relationship between the frequency and theintensity of the phase modulation of the jitter of the dot clock S14;FIG. 3B is a view showing the relationship between the litter transferand the frequency of the PLL circuit 5; FIG. 3C is a view showing therelationship between the phase modulation intensity and the frequency ofthe jitter contained in the serial signal S4; FIG. 3D is a view showingthe relationship between the relative tracking error and the frequencyof the PLLC circuit 6; and FIG. 3E is a view showing the relationshipbetween the tracking error and the frequency of the PLL circuit 6.

In the digital video signal transmission apparatus 1, first, the dotclock signal S14 having the modulation intensity of the litter as shownin FIG. 3A is input to the PLL circuit 5 shown in FIG. 1.

Here, the PLL circuit 5 has LPF (low pass filter) characteristics asshown in FIG. 3B and, in addition, sets the cutoff frequency BWP₁ to 10times or less of the frequency f_(HSYNC) of the horizontalsynchronization signal; therefore, the large amount of jitter near thefrequency f_(HSYNC) of the horizontal synchronization signal containedin the dot clock signal S14 show in FIG. 3A is greatly attenuated, and atransmission clock signal S5 obtained by multiplying the dot clocksignal S14 in which the jitter was attenuated by N is generated.

This transmission clock signal S5 is output to the parallel/serialconverter 2.

Then, in the parallel/serial converter 2, the digital R signal S10, thedigital G signal S11, the digital B signal S 12, and the SYNC(synchronization) signal S13 comprising the digital video signal S9 areinput in parallel. These signals are subjected to parallel/serialconversion based on the transmission clock signal S5 and the dot clocksignal S14 to generate the serial signal S2. At this time, since atransmission clock signal S6 in which the jitter contained in the serialsignal S2 is improved as shown in FIG. 3C.

Then, the serial signal S2 is transmitted to the serial/parallelconverter 3 and the PLL circuit 6 via the transmission cable 4.

Then, in the PLL circuit 6, the transmission clock signal S6 isextracted by tracking the transmission clock signal contained in theserial signal S2, This transmission clock signal S6 is output to theserial/parallel converter 3 and the frequency divider 7.

At this time, since the PLL circuit 6 has, for example, a cutofffrequency BWP₂ to 10 times or more the frequency f_(HSYNC) of thehorizontal synchronization signal of the video signal 9, as mentionedabove as shown in FIGS. 3D and 3E, the transmission clock signal S6tracks the phase modulation of the transmission clock signal containedin the serial signals very well. For this reason, the occurrence oftransmission error is suppressed.

The transmission clock signal 86 is divided in frequency by N at thefrequency divider 7, and the dot clock signal S7 is generated. The dotclock signal S7 is output to the serial/parallel converter 3.

Then, in the serial/parallel converter 3, the serial signal 84 receivedvia the transmission cable 4 is converted from serial to parallel basedon the transmission clock signal S6 and the dot clock signal S7, and thedigital R signal S20, the digital G signal S21, the digital B signalS22, and the SYNC (synchronized) signal S23 comprising the digital videosignal S19 are output in parallel.

The present invention is not limited to the above embodiment.

For example, in the embodiment, as the phase modulation intensity of thejitter contained in the dot clock signal S14, the case shown in FIG. 3Awas exemplified, but the effect can be similarly exhibited in casesother than this was well.

Also, the above embodiment, the cutoff frequency BWP₁ of the PLL circuit5 was set 1/10 times or less of the frequency f_(HSYNC) of thehorizontal synchronization signal, the cutoff frequency BWP₁ can beanother frequency too, so far as it is lower than the frequencyf_(HSYNC.)

Further, in the above embodiment, the cutoff frequency BWP₂ of the PLLcircuit 6 was set to 10 times the frequency f_(HSYNC) of the horizontalsynchronization signal, but the cutoff frequency BWP₂ can be anotherfrequency too so far as it is higher than the frequency f_(HSYNC.)

As explained above, according to the video signal transmission apparatusof the present invention, the effect of the strong phase modulationhaving a frequency in this vicinity of the frequency of the horizontalsynchronized signal is suppressed, and thus the digital video signal canbe correctly transmitted.

INDUSTRIAL APPLICABILITY

The video signal transmission apparatus of the present invention can beused when transmitting a multi-bit, digital, video signal serially to aliquid crystal display or other display which receives as input adigital signal.

What is claimed is:
 1. A video signal transmission apparatus,comprising: a first PLL circuit having a first cutoff frequency lowerthan a frequency of a horizontal synchronization signal contained in adigital video signal, having the characteristic of causing attenuationof a phase modulation component of a frequency higher than the firstcutoff frequency, and generating a first transmission clock signal of afrequency of N (integer of 2 or more) times a first dot clock signal foridentifying one pixel's worth of data of the digital video signal andphase locked looped to the first dot clock signal; a first conversionmeans for generating a serial signal from a plurality of parallel inputelement signals comprising the digital video signal based on the firstdot clock signal and the first transmission clock signal; a transmissionchannel for transmitting the serial signal; a second PLL circuit havinga second cutoff frequency higher than the frequency of the horizontalsynchronization signal, tracking a phase modulation of a frequency lowerthan the second cutoff frequency, and generating a second transmissionclock signal from said serial signal input via the transmission channel;a frequency division circuit for dividing the second transmission clocksignal to 1/N to generate a second dot clock signal; and a secondconversion means for generating a plurality of element signals to beoutput in parallel from a serial signal input through the transmissionchannel based on the second dot clock signal and the second transmissionclock signal.
 2. A video signal transmission apparatus as set forth inclaim 1, wherein the first PLL circuit attenuates a phase modulationcomponent contained in the first dot clock signal more the higher thefrequency in a frequency region higher than the first cutoff frequency.3. A video signal transmission apparatus as set forth in claim 1,wherein the second PLL circuit has less of a tracking error the lowerthe frequency in a frequency region lower than the second cutofffrequency.
 4. A video signal transmission apparatus as set forth inclaim 2, wherein the second PLL circuit has less of a tracking error thelower the frequency in a frequency region lower than the second cutofffrequency.
 5. A video signal transmission apparatus as set forth inclaim 1, wherein the plurality of element signals are digital colorsignals and a synchronization signal.
 6. A video signal transmissionapparatus as set forth in claim 1, wherein said N is 4, 18, 24, 28, 30,or
 32. 7. A video signal transmission apparatus as set forth in claim 1,wherein the transmission channel is a cable.
 8. A video signaltransmission apparatus for generating and transmitting a serial signalfrom a plurality of parallel input element signals comprising a digitalvideo signal, comprising: a PLL circuit having a cutoff frequency lowerthan a frequency of a horizontal synchronization signal contained in thedigital video signal, having the characteristic of causing attenuationof a phase modulation component of a frequency higher than the cutofffrequency, and generating a transmission clock signal of a frequency ofN (integer of 2 or more) times a dot clock signal for identifying onepixel's worth of data of the digital video signal and phase lockedlooped to the dot clock signal and a conversion means for generating aserial signal from a plurality of parallel input element signalscomprising the digital video signal based on the dot clock signal andthe transmission clock signal.
 9. A video signal transmission apparatusas set forth in claim 8, wherein the PLL circuit attenuates a phasemodulation component contained in the dot clock signal more the higherthe frequency in a frequency region higher than the cutoff frequency.10. A video signal transmission apparatus as set forth in claim 8,wherein the plurality of element signals are digital color signals and asynchronization signal.
 11. A video signal transmission apparatus forreceiving a serial signal generated from a plurality of parallel inputelement signals comprising a digital video signal through a transmissionchannel based on a first transmission clock signal phase locked loopedto a first dot clock signal, attenuated in phase modulation component ofa frequency higher than a first cutoff frequency lower than a frequencyof a horizontal synchronization signal contained in the digital videosignal, identifying one pixel's worth of data of a digital video signaland having a frequency of N (an integer of 2 or more) times a first dotclock signal and on said first dot signal, comprising: a PLL circuithaving a second cutoff frequency higher than the frequency of thehorizontal synchronization signal, tracking phase modulation of afrequency lower than the second cutoff frequency, and generating asecond transmission clock signal from said serial signal input throughthe transmission channel, a frequency division circuit for dividing thesecond transmission clock signal to 1/N to generate a second dot clocksignal, and a conversion means for generating a plurality of paralleloutput element signals from a serial signal input through saidtransmission channel based on said second dot clock signal and saidsecond transmission clock signal.
 12. A video signal transmissionapparatus as set forth in claim 11, wherein the PLL circuit has less ofa tracking error the lower the frequency in a frequency region lowerthan the second cutoff frequency.
 13. A video signal transmissionapparatus as set forth in claim 11, wherein said plurality of elementsignals are digital color signals and a synchronization signal.